1. Field of the Invention
The present invention relates to a display device, and more particularly to a display device having thin film transistors.
2. Description of the Related Art
This type of display device is configured such that a plurality of pixels is arranged in a display part thereof in a matrix array, respective pixel rows are sequentially selected by turning on the thin film transistors provided to the respective pixels in response to a scanning signal supplied via a gate signal line, and at timing of such selection, a video signal is supplied to the respective pixels of the pixel row via a drain signal line to which the pixels of opposing pixel row are connected in common.
Further, a drive circuit which drives the display device may be formed around the display region which is formed of a mass of the respective pixels, and the drive circuit also includes the thin film transistor.
The thin film transistor is constituted of, for example, a gate electrode which is connected to the gate signal line, a semiconductor layer which is formed astride the gate electrode via an insulation film, a drain electrode which is connected with the drain signal line and is formed on the semiconductor layer, and a source electrode which is connected with the pixel electrode and is formed on the semiconductor layer in an opposed manner with the drain electrode.
The semiconductor layer arranged between the drain electrode and the source electrode functions as a channel region, and an electric current is supplied between the drain electrode and the source electrode via the channel region in response to a voltage applied to the gate electrode.
Further, the thin film transistor is usually configured such that an electric field attenuation region is formed between the channel region and the drain electrode as well as between the channel region and the source electrode. The electric field attenuation region is formed of a semiconductor layer of relatively high resistance, and due to the provision of the electric field attenuation region, it is possible to prevent the generation of concentration of electric field between the channel region and the drain electrode as well as between the channel region and the source electrode thus attenuating an OFF current.
As such an electric field attenuation region, there has been known an electric field attenuation region of the structure which arranges the electric field attenuation region between a channel region and a drain region of the semiconductor layer as well as between the channel region and a source region in plane, and an electric field attenuation region of the structure which vertically arranges the electric field attenuation region in an overlapping manner with the drain electrode and the source electrode. The structure of the latter electric field attenuation region is disclosed in detail in JP-A-2001-102584, for example.